The present invention relates to an integrated circuit device, and particularly to one with a self-diagnosis circuit mounted thereon. In particular, this invention relates to a large scale integrated circuit device having a hardware diagnosis function for a disk array apparatus. The invention further relates to a method for diagnosing a large scale integrated circuit device for a disk array apparatus, and in particular, an effective method for applying the diagnosis of a disk array apparatus to an integrated circuit device before shipment of the integrated circuit device.
Hardware diagnosis of a disk array apparatus conventionally has been conducted by either of the following methods: individually performing hardware diagnosis of the respective packages constituting the disk array apparatus before their shipment as the disk array apparatus, by using a package tester (such as an in-circuit tester), assembling the packages into the disk array apparatus, and then making the entire disk array apparatus operate and performing hardware diagnosis of the disk array apparatus as a whole; or executing a special test program in a disk array apparatus after shipment and performing hardware diagnosis in a state where the respective packages are incorporated in the disk array apparatus.
As an example of the technique of diagnosing each functional block of a semiconductor device before shipping an integrated circuit device, a self-diagnosis device for a semiconductor device is suggested, wherein each functional block is equipped with a self-diagnosis circuit of a BIST (Built-in Self Test) system, a self-diagnosis controller sends diagnosis conditions to each functional block in accordance with a diagnosis program previously stored in the memory, and whether the semiconductor device is normal or abnormal is displayed based on the diagnosis result from the self-diagnosis circuit of each functional device (see JP-A-2003-68865).
FIG. 20 shows an example of the self-diagnosis device using the BIST system. In this case, of a plurality of flip-flops FF constituting circuit blocks 400 and 402, the three-row flip-flops FF constituting the circuit block 400 are connected, via scan chains, as CLKA domain flip-flops; the three-row flip-flops FF constituting the circuit block 402 are connected, via scan chains, as CLKB domain flip-flops; pattern generation circuits 404 and 406 input patterns to the flip-flops FF in each row of the functional blocks 400 and 402 in accordance with clock signals; the test results output from the circuit blocks 400 and 402 are compressed in compression circuits 408 and 410; a BIST control circuit 412 checks each compressed test result against an expected value; and the check results are output from an I/O terminal 414.
However, as shown in FIG. 21, even if clock signals for the CLKA domain and the CLKB domain according to a CTS (Clock Tree Synthesis) system are applied to the flip-flops FF belonging to the circuit blocks 400 and 402 respectively, an AC test (an alternating current characteristic performance test for examining operating characteristics (delay) of a circuit, and circuit functions by applying a signal indicating the actual use state to the circuit) between different clock domains cannot be conducted. Even if a defect due to delay exists in part of the circuit blocks 400 and 402, the defect cannot be detected. Meanwhile, when a hardware test is conducted after mounting a large scale integrated circuit device (LSI) for a disk array apparatus in a disk array apparatus, a method of confirming whether or not a defect exists in an LSI 504 (test target) including a data transfer processor is adopted, as shown in FIG. 22, by the following steps of: storing a test program on a ROM 500; loading the test program stored on the ROM 500 to a CPU 502; generating a test pattern, including an address (ADR) and data (DATA), at the CPU 502; inputting the test pattern to the LSI 504; conducting a data transfer test in the LSI 504 based on the data entered to the LSI 504; and having the CPU 302 compare (COMP) the test result with an expected value for the target. According to this test, whether a defect exists or not can be confirmed by operating not only the synchronous part, but also the asynchronous part (circuit bloc) of the LSI 504.
Moreover, JP-A-2005-301565 suggests that hardware diagnosis of a disk array apparatus after shipment be conducted is a short time while the disk array apparatus is operating.
Various methods for performing hardware diagnosis of a disk array apparatus after shipment have been suggested. However, as a method for performing hardware diagnosis before shipment, there is only one method—performing hardware diagnosis of each package individually by using a package tester. There has been no method for performing hardware diagnosis before mounting (or assembling) the apparatus in consideration of the active state of the apparatus.